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PRELIMINARY
CY7B9532V
SONET OC-48 Transceiver
Features
* * * * * * * * * SONET OC-48 operation Full Bellcore and ITU jitter compliance 2.488-GBaud serial signaling rate Multiple selectable loopback/loop-through modes Single 155.52-MHz reference clock Transmit FIFO for flexible data interface clocking 16-bit parallel-to-serial conversion in transmit path Serial to 16-bit parallel conversion in receive path Synchronous HSTL parallel interface -- Drives Low-Z transmission lines -- No resistors for short (70-mm) interconnect * * * * * * * * -- LVPECL compliant Internal transmit and receive PLLs Differential CML serial input -- Internal termination and DC-restoration Differential CML serial output -- Source matched for 50 transmission lines Direct interface to standard fiber-optic modules Single +3.3V supply (1.3W typ.) 120-pin 14 mm x 14 mm TQFP Standby power-saving mode for inactive loops 0.25 BiCMOS technology FIFO to allow flexible transfer of data between the SONET processor and the transmit serializer. As each 16-bit word is read from the transmit FIFO, it is serialized and sent out the high-speed differential line driver at a rate of 2.488 Gbits/second. Receive Path As serial data is received at the differential line receiver, it is passed to a clock and data recovery (CDR) phase-locked loop (PLL) which extracts a precision low-jitter clock from the transitions in the data stream. This bit-rate clock is then used to sample the data stream and receive the data. Every 16 bittimes, a new word is presented at the receive parallel interface along with a clock. Parallel Interface The parallel I/O interface supports high-speed bus communications using HSTL signaling levels to minimize both power consumption and board landscape. The HSTL outputs are capable of driving unterminated transmission lines of greater than 70 mm, and terminated 50 transmission lines of more than twice that length. The CY7B9532V Transceiver's parallel HSTL I/O can also be configured to operate at LVPECL signaling levels. This can all be done externally by changing VDDQ, VREF, and creating a simple circuit at the termination of the receiver's parallel I/O interface. Clocking The source clock for the transmit data path is selectable from either the recovered clock or an external BITS (Building Integrated Timing Source) reference clock. The low jitter of the CDR PLL allows loop-timed operation of the transmit data path while still meeting all Bellcore and ITU jitter requirements. Multiple loopback and loop-through modes are available for both diagnostic and normal operation. For systems containing redundant SONET rings that are maintained in standby, the CY7B9532V may also be dynamically powered down to conserve system power.
Functional Description
The CY7B9532V SONET OC-48 Transceiver is a communications building block for high-speed SONET data communications. It provides complete parallel-to-serial and serial-to-parallel conversion in a single chip, optimized for full SONET compliance. Transmit Path New data is accepted at the 16-bit parallel transmit interface at rate of 155.52 MHz. This data is passed to a small integrated SONET Data Processor
16
CY7B9532V
TXD[15:0] TXCLKI FIFO_RST FIFO_ERR TXCLKO RXD[15:0] RXCLK LOOPTIME DIAGLOOP LOOPA LINELOOP RESET PWRDN LOCKREF LFI
System or Telco Bus
Transmit Data Interface 16
REFCLK
2
155.52 MHz BITS Time Reference
Host Bus Interface
Receive Data Interface
Data & Clock Direction Control
IN+ IN- SD OUT- OUT+
Serial Data
Serial Data
RD+ RD- SD TD- TD+
Optical XCVR
Optical Fiber Links
Status & System Control
Figure 1. CY7B9532V System Connections
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 March 13, 2000
PRELIMINARY
CY7B9532V Logic Block Diagram
(155.52 MHz) TXCLKI TXD[15:0] FIFO_RST 16 FIFO_ERR TXCLKO (155.52 MHz) REFCLK (155.52 MHz) RXCLK
CY7B9532V
RXD[15:0]
16
Input Register
TX PLL X16
Output Register /16 Shifter Recovered Bit-Clock RX CDR PLL Lock-to-Ref Retimed Data
FIFO
/16 TX Bit-Clock
Shifter
LOOPTIME DIAGLOOP
LINELOOP LOOPA
Lock-to-Data/ Clock Control Logic
OUT
PWRDN LOCKREF
SD
LFI
RESET
IN
2
PRELIMINARY
Pin Configuration
Top View
NC NC RXCP2 RXCN2 NC RXCP1 RXCN1 NC VCCQ VSSQ VCCQ IN+ IN- VSSQ CM_SER VCCQ OUT- OUT+ VCCQ VSSQ VCCQ NC VSSQ NC VSSQ VCCQ NC NC
CY7B9532V
NC
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101
100 99 98 97 96 95 94 93 92 91
NC
LFI RESET DIAGLOOP LINELOOP LOOPA VSSN VCCN VSSN VSSN SD LOCKREF RXD[0] RXD[1] RXD[2] RXD[3] VSSN VDDQ RXD[4] RXD[5] RXD[6] RXD[7] VSSN VDDQ RXCLK VSSN VDDQ NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
CY7B9532
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60
NC VCCQ VSSQ REFCLK+ REFCLK- NC LOOPTIME PWRDN VSSN VCCN VSSN TXCLKO VSSN VDDQ TXD[0] TXD[1] TXD[2] TXD[3] VCCQ VSSQ VCCN VSSN TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9] TXD[10] TXD[11]
NC NC NC NC NC RXD[8]
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C VCC Supply Voltage to Ground Potential........ -0.5V to +4.2V VDDQ Supply Voltage to Ground Potential ..... -0.5V to +3.0V DC Voltage Applied to HSTL Outputs in High-Z State ...................................... -0.5V to VDDQ+0.5V DC Voltage Applied to Other Outputs in High-Z State .........................................-0.5V to VCC+0.5V
VSSN VDDQ RXD[12] RXD[13] RXD[14] RXD[15] VSSN VDDQ VCCN VSSN FIFO_ERR FIFO_RST TXD[15] TXD[14] TXD[13] TXD[12] TXCLKI VSSN VCCN VREF
VSSQ
RXD[9] RXD[10] RXD[11]
Output Current into LVTTL Outputs (LOW) ................. 30 mA DC Input Voltage ..................................... -0.5V to VCC+0.5V Static Discharge Voltage ...............................................> 2001 V (per MIL-STD-883, Method 3015) Latch-Up Current...........................................................> 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDDQ 1.6V to 1.4V 1.6V to 1.4V VCC 3.3V 10% 3.3V 5%
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PRELIMINARY
Pin Descriptions
CY7B9532V OC-48 SONET Transceiver Name TXDA[15:0] I/O Characteristics HSTL inputs, sampled by TXCLKI HSTL Clock input HSTL Clock output HSTL output, synchronous HSTL Clock output Signal Description Transmit Path Signals
CY7B9532V
Parallel Transmit Data Inputs. A 16-bit word, sampled by TXCLKI. TXD[15] is the most significant bit (the first bit transmitted). Parallel Transmit Data Input Clock Transmit Clock Output. Divide by 16 of the selected transmit bit-rate clock Parallel Receive Data Output. These outputs change following RXCLKO. RXD[15] is the most significant bit of the output word, and is received first on the serial interface. Receive Clock Output. Divide by 16 of the bit-rate clock extracted from the received serial stream.
TXCLKI TXCLKO RXD[15:0]
Receive Path Signals
RXCLK
Device Control and Status Signals REFCLK Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and input receive PLLs. A derivative of this input clock may also be used to clock the transmit parallel interface. LVTTL output Line Fault Indicator. When LOW, this signal indicates that the selected receive data stream has been detected as invalid by either a LOW input on SD, or by the receive VCO being operated outside its specified limits. Reset for all logic functions except the transmit FIFO. Receive PLL Lock to Reference. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream. Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream. Transmit FIFO Error. When HIGH the transmit FIFO has either under or overflowed. The FIFO must be reset to clear the error indication. Transmit FIFO Reset. When LOW, the in and out pointers of the transmit FIFO are set to maximum separation. Device Power Down. When LOW, the logic and drivers are all disabled and placed into a standby condition where only minimal power is dissipated. Common Mode Termination. Capacitor shunt to VSS for common mode noise. Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Positive) Receive Loop Filter Capacitor (Positive) VDDQ/2.
LFI
RESET LOCKREF SD FIFO_ERR FIFO_RST PWRDN
LVTTL input LVTTL input LVTTL input LVTTL output LVTTL input LVTTL input
Receive Path Signals CM_SER RXCN1 RXCN2 RXCP1 RXCP2 VREF Analog Analog Analog Analog Analog HSTL Analog Reference LVTTL input
Loop Control Signals DIAGLOOP Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive clock and data recovery and presented at the RXD[15:0] outputs. When LOW, received serial data is routed through the receive clock and data recovery and presented at the RXD[15:0] outputs. Line Loopback Control. When HIGH, received serial data is looped back from receive to transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data passed to the OUT line driver is controlled by LOOPA. When both LINELOOP and LOOPA are LOW, the data passed to the OUT line driver is generated in the transmit shifter.
LINELOOP
LVTTL input
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PRELIMINARY
Pin Descriptions (continued)
CY7B9532V OC-48 SONET Transceiver Name LOOPA I/O Characteristics LVTTL input Signal Description
CY7B9532V
Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial data is looped back from receive input buffer to transmit output buffer, but is not routed through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the OUT line driver is controlled by LINELOOP. Loop Time Mode. When HIGH, the extracted receive bit-clock replaces transmit bitclock. When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock. Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable of driving terminated 50 transmission lines or commercial fiber-optic transmitter modules. Differential Serial Data Input. This differential input accept the serial data stream for deserialization and clock extraction. +3.3V Supply (for digital and low-speed I/O functions) Signal and Power Ground (for digital and low-speed I/O functions) +3.3V Quiet Power (for analog functions) Quiet Ground (for analog functions) +1.5V Supply for HSTL Outputs Transmit PLL Clock Multiplier The Transmit PLL Clock Multiplier accepts a 155.52-MHz external clock at the REFCLK input, and multiplies that clock by 16 to generate a bit-rate clock for use by the transmit shifter. The operating serial signaling rate and allowable range of REFCLK frequencies is listed in Table 7. The REFCLK input is a standard PECL input. Serializer The parallel data from the phase-align buffer is passed to the Serializer which converts the parallel data to serial data using the bit-rate clock generated by the Transmit PLL clock multiplier. TXD[15] is the most significant bit of the output word, and is transmitted first on the serial interface. Serial Output Driver The serial interface Output Driver makes use of high-performance differential CML (Current Mode Logic) to provide a source-matched driver for the transmission lines. This driver receives its data from the Transmit Shifters or the receive loopback data. The outputs have signal swings equivalent to that of standard PECL drivers, and are capable of driving ACcoupled optical modules or transmission lines.
LOOPTIME
LVTTL input
Serial I/O OUT Differential CML output Differential CML input Power Ground
IN Power VCCN VSSN VCCQ VSSQ VDDQ
CY7B9532 Operation
The CY7B9532 is a highly configurable device designed to support reliable transfer of large quantities of data, using highspeed serial links. It performs necessary clock and data recovery, clock generation, serial-to-parallel conversion, and parallel-to-serial conversion. CY7B9532 also provides various loopback functions.
CY7B9532 Transmit Data Path
Operating Modes The transmit path of the CY7B9532 supports 16-bit-wide data paths. Phase-Align Buffer Data from the input register is passed to a phase-align buffer (FIFO). This buffer is used to absorb clock phase differences between the transmit input clock and the internal character clock. Initialization of the phase-align buffer takes place when the FIFO_RST input is asserted LOW. When FIFO_RST is returned HIGH, the present input clock phase relative to TXCLKI is set. Once set, the input clock is allowed to skew in time up to half a character period in either direction relative to REFCLK; i.e., 180. This time shift allows the delay path of the character clock (relative to REFLCK) to change due to operating voltage and temperature, while not effecting the design operation. FIFO_RST is an asynchronous input. FIFO_ERR is the transmit FIFO Error indicator. When HIGH, the transmit FIFO has either under or overflowed. The FIFO can be externally reset to clear the error indication or if no action is taken the internal clearing mechanism will clear the FIFO in 9 clock cycles. When the FIFO is being reset, the output data is 1010.
CY7B9532 Receive Data Path
Serial Line Receivers A differential line receiver, IN is available for accepting the input serial data stream. The serial line receiver inputs can accommodate high wire interconnect and filtering losses or transmission line attenuation (VDIF > 125 mV, or 250 mV peakto-peak differential) and can be AC-coupled to +3.3V or +5V powered fiber-optic interface modules. The common-mode tol-
5
PRELIMINARY
erance of these line receivers accommodates a wide range of signal termination voltages. Lock to Data Control Line Receiver routed to the clock and data recovery PLL is monitored for * status of signal detect (SD) pin * status of LOCKREF pin * received data stream outside normal frequency range (200 ppm) This status is presented on the LFI (Link Fault Indicator) output, which changes asynchronously in the cases when SD or LOCKREF goes from HIGH to LOW. Otherwise, it changes synchronous to the REFCLK. Clock/Data Recovery The extraction of a bit-rate clock and recovery of data bits from received serial stream is performed by a Clock/Data Recovery (CDR) block. The clock extraction function is performed by high-performance embedded phase-locked loop (PLL) that tracks the frequency of the incoming bit stream and aligns the phase of the internal bit-rate clock to the transitions in the selected serial data stream. CDR accepts a character-rate (bit-rate / 16) reference clock on the REFCLK input. This REFCLK input is used to ensure that the VCO (within the CDR) is operating at the correct frequency (rather than some harmonic of the bit-rate), to improve PLL acquisition time, and to limit unlocked frequency excursions of the CDR VCO when no data is present at the serial inputs. Regardless of the type of signal present, the CDR will attempt to recover a data stream from it. If the frequency of the recovered data stream is outside the limits set by the range controls, the CDR PLL will track REFCLK instead of the data stream. When the frequency of the selected data stream returns to a valid frequency, the CDR PLL is allowed to track the received data stream. The frequency of REFCLK is required to be within 200 ppm of the frequency of the clock that drives the REFCLK signal of the remote transmitter to ensure a lock to the incoming data stream. For systems using multiple or redundant connections, the LFI output can be used to select an alternate data stream. When an LFI indication is detected, external logic can toggle selection of the input device. When such a port switch takes place, it is necessary for the PLL to re-acquire lock to the new serial stream. External Filter The CDR circuit uses external capacitors for the PLL filter. A 0.1-F capacitor needs be connected between RXCN1 and RXCP1. Similarly a 0.1-F capacitor needs to be connected between RXCN2 and RXCP2. The recommended capacitors for the external filters are 0805 NPO or 0603 NPO. Deserializer The CDR circuit extracts bits from the serial data stream and clocks these bits into the Deserializer at the bit-clock rate. The Deserializer converts serial data into parallel data. RXD[15] is the most significant bit of the output word and is received first on the serial interface. Loopback/Timing Modes
CY7B9532V
CY7B9532V supports various loopback modes as described below. Facility Loopback (line loopback with retiming) When the LINELOOP signal is set HIGH, the Facility Loopback mode is activated and the high-speed serial receive data (IN) is presented to the high-speed transmit output (OUT) after retiming. In Facility Loopback mode, the high-speed receive data (IN) is also converted to parallel data and presented to the low-speed receive data output pins (RXD[15:0]). The receive recovered clock is also divided down and presented to the low speed clock output (RXCLK). Equipment Loopback (diagnostic loopback with retiming) When the DIAGLOOP signal is set HIGH, transmit data is looped back to the RX PLL, replacing IN. Data is looped back from the parallel TX inputs to the parallel RX outputs. The data is looped back at the internal serial interface and goes through transmit shifter and the receive CDR. SD is ignored in this mode. Line Loopback Mode (non-retimed data) When the LOOPA signal is set HIGH, the RX serial data is directly buffered out to the transmit serial data. The data at the serial output is not retimed. Loop Timing Mode When the LOOPTIME signal is set HIGH, the TX PLL is bypassed and receive bit-rate clock is used for transmit side shifter. Reset Modes ALL logic circuits in the device can be reset using RESET and FIFO_RST signals. When RESET is set LOW, all logic circuits except FIFO are internally reset. When FIFO_RST is set LOW, the FIFO logic is reset. Power-down Mode CY7B9532 provides a global power-down signal PWRDN. When LOW, this signal powers down the entire device to a minimal power dissipation state. RESET and FIFO_RST signals should be asserted LOW along with PWRDN signal to ensure low power dissipation. PECL Compliance The CY7B9532V HSTL parallel I/O can be configured to LVPECL compliance with slight termination modifications. On the transmit side of the transceiver, the TXD[15:0] and TXCLK can be made LVPECL compliant by setting VREF (reference voltage of a LVPECL signal) to VCC-1.33 volts. To emulate a LVPECL signal on the receiver side of the transceiver, the transmission lines need to be terminated with the Thevenin equivalent of Zo at LVPECL ref. Next the signal is attenuated using a series resistor at the driver end of the line to reduce the HSTL voltage swing level to an LVPECL swing level (see Figure 6). This circuit needs to be used on all 16 RXD[15:0] pins and the RXCLK. The voltage divider has been calculated assuming the system is built with 50 transmission lines.
6
PRELIMINARY
DC Specifications
Table 1. DC Specifications - LVTTL Parameter LVTTL Outputs VOHT VOLT IOS LVTTL Inputs VIHT VILT IIHT IILT Capacitance CIN COUT Input Capacitance Output Capacitance VCC = Max. @ f = 1 MHz VCC = Max. @ f = 1 MHz Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Low = 2.0V High = VCC + 0.5V Low = -3.0V High = 0.8 VCC = Max. VIN = VCC VCC = Max. VIN = 0V 2.0 -0.3 Output HIGH Voltage Output LOW Voltage Output Short Circuit Current VCC = Min., IOH = -10.0 mA VCC = Min., IOL = 10.0 mA VOUT = 0V -20 2.4 Description Test Conditions Min.
CY7B9532V
Max.
Unit V
0.4 -90 VCC - 0.3 0.8 50 -50
V mA V V A A
5 7
pF pF
Table 2. DC Specifications - Power Parameter Power ICC1 ISB Active Power Supply Current Standby Current 400 1 mA mA Description Test Conditions Min. Typical Unit
Table 3. DC Specifications - Differential PECL Input (REFCLK) Parameter VINSGLE VDIFFE VIEHH VIELL IIEH IIEL Capacitance CINE Input Capacitance 4 pF Description Input Single-ended Swing Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current VIN = VIEHH Max. VIN = VIELL Min. -200 Test Conditions Min. 200 400 VCC - 1.2 VCC - 2.0 Max. 600 1200 VCC - 0.3 VCC - 1.45 750 Unit mV mV V V A A
Receiver PECL Compatible Inputs
7
PRELIMINARY
Table 4. DC Specifications - Differential CML Parameter VOHC VOLC VDIFFOC VSGLCO VINSGLC VDIFFC VICHH VICLL IICH IICL Capacitance CINC Input Capacitance Description Output HIGH Voltage (VCC Referenced) Output LOW Voltage (VCC Referenced) Output Differential Swing Output Single-ended Voltage Input Single-ended Swing Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current VIN = VICHH Max. VIN = VICLL Min. 1.2 Test Conditions Min.
CY7B9532V
Max.
Unit V V mV mV mV mV V V mA mA pF
Transmitter CML Compatible Outputs 100 differential load VCC - 0.5 VCC - 0.2 100 differential load VCC - 1.1 VCC - 0.7 100 differential load 100 differential load 560 280 125 250 1500 750 600 1200 VCC 47 20 4
Receiver CML Compatible Inputs
Table 5. DC Specifications - HSTL Parameter HSTL Outputs VOHH VOLH IOSH HSTL Inputs VIHH VILH IIHH IILH Capacitance CINH COUTH Input Capacitance Output Capacitance VDDQ = Max. @ f = 1 MHz VDDQ = Max. @ f = 1 MHz 5 7 pF pF Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current VDDQ = Max. VIN = VDDQ VDDQ = Max. VIN = 0V VREF + 0.1 VDDQ + 0.3 -0.3 VREF - 0.1 50 -40 V V A A Output HIGH Voltage Output LOW Voltage Output Short Circuit Current VCC = Min., IOH= -4.0 mA VCC = Min., IOL= 4.0 mA VOUT = 0V VDDQ - 0.4 0.4 100 V V mA Description Test Conditions Min. Max. Unit
8
PRELIMINARY
AC Specifications
Table 6. AC Specifications - HSTL Parallel Interface Parameter tTS tTXCLKI tTXCLKID tTXCLKR tTXCLKF tTXDS tTXDH tRS tRXCLKO tRXCLKOD tRXCLKOR tRXCLKOF tRXDS tRXDH Description TXCLK Frequency (must be frequency coherent to REFCLK when used as the TXPLL clock source) TXCLKI Period TXCLKI Duty Cycle TXCLK Rise Time TXCLK Fall Time Min. 154.5 6.38 40 0.3 0.3 1 1 154.5 6.38 43 0.3 0.3 2.5 2
CY7B9532V
Max. 156.5 6.47 60 1.5 1.5
Unit MHz ns % ns ns ns ns
of TXCLKI Write Data Hold from of TXCLK
Write Data Set-up to RXCLK Frequency RXCLKO Period RXCLKO Duty Cycle RXCLKO Rise Time RXCLKO Fall Time Recovered Data Set-up to of RXCLKO Recovered Data Hold from of RXCLKO
156.5 6.47 57 1.5 1.5
MHz ns % ns ns ns ns
Table 7. AC Specifications - REFCLK Parameter tREF tREFP tREFD tREFT tREFR tREFF REFCLK Input Frequency REFCLK Period REFCLK Duty Cycle REFCLK Frequency Tolerance (relative to received serial data) REFCLK Rise Time REFCLK Fall Time Description Min. 154.5 6.38 35 -100 0.3 0.3 Max. 156.5 6.47 75 +100 1.5 1.5 Unit MHz ns % ppm ns ns
Table 8. AC Specifications - CML Serial Outputs Parameter tRISE tFALL tTJ Description CML Output Rise Time (20-80%, 100 balanced load) CML Output Fall Time (80-20%, 100 balanced load) Total Output Jitter (p-p) Total Output Jitter (rms) Min. 60 60 Max. 170 170 0.1 0.01 Unit ps ps UI UI
9
PRELIMINARY
AC Test Loads and Waveforms
3.3V OUTPUT R1=330 R2=510 CL 10 pF (Includes fixture and probe capacitance) R1 CL R2 OUT+ OUT- RL RL =100
CY7B9532V
(a) TTL AC Test Load
(b) CML AC Test Load
1.5V OUTPUT R1=100 R2=100 CL 7 pF (Includes fixture and probe capacitance) R1 CL R2
(a) HSTL AC Test Load
3.0V Vth=1.4V GND < 1 ns 2.0V 0.8V
3.0V 2.0V 0.8V Vth=1.4V < 1 ns 80% 20% 250 ps
VICHH 80% 20% V ICLL 250 ps
(a) LvTTL Input Test Waveform
(b) CML Input Test Waveform
VIHH Vth=0.75V VIHL < 1 ns < 1 ns 80% 20% 80% 20% 80% Vth=0.75V 20% 250 ps
VIEHH 80% 20% VIELL 250 ps
(c) HSTL Input Test Waveform
(d) LVPECL Input Test Waveform
10
PRELIMINARY
CY7B9532
Zo=50 OUT+ OUT- Zo=50
CY7B9532V
Limiting Amp
0.1 F
IN+ IN-
100
0.1 F
Figure 2. Serial Input Termination
CY7B9532
Zo=50
0.1 FOUT+
OUT-
100
Zo=50
0.1 F
Figure 3. Serial Output Termination
CY7B9532 1.5V R1 HSTL OUTPUT R2
Zo=50 HSTL INPUT
Figure 4. TXCLKO/ RXCLK Termination
CY7B9532
HSTL INPUT
Zo=50
HSTL OUTPUT
Figure 5. RXD[15:0] Termination
3.3 VCC RPU R1 50 Transmission Line
RXD[15:0] & RXCLK
PECL INPUT
R1 = 137, RPU = 80.6, RPD = 121
RPD
Figure 6. LVPECL Compliant Termination
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PRELIMINARY
Switching Waveforms
Transmit Interface Timing
CY7B9532V
tTXCLK tTXCLKH
TXCLK
tTXCLKL
tTXDS
TXDx[15:0]
tTXDH
Receive Interface Timing tRXCLKP tRXCLKH
RXCLK
tRXCLKL
tRXDS
RXD[15:0]
tRXDH
Ordering Information
Speed Standard Standard Ordering Code CY7B9532-AC CY7B9532-AI Package Name A120 A120 120-pin TQFP 120-pin TQFP Package Type Operating Range Commercial Industrial
Document #: 38-00894
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PRELIMINARY
CY7B9532V
Package Diagram
120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) A120
51-85100
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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